Field of the Invention
This invention relates to a driving circuit of a display, especially to a level shifter applied to a driving circuit of a display.
Description of the Related Art
In general, the driving circuit of the display performs multi-power domain boost on input voltage signals through level shifters. Please refer to FIG. 1 and FIG. 2. FIG. 1 illustrates a schematic diagram of the level shifter of the conventional driving circuit; FIG. 2 illustrates a detailed circuit diagram of the level shifter of FIG. 1.
As shown in FIG. 1, the conventional level shifter 7 can include a first stage of level shifting unit 71 and two second stage of level shifting units 72 and 73. The first stage of level shifting unit 71 is coupled between the ground voltage AGND/half-operating voltage hAVDD and the first middle voltage VCL1; the second stage of level shifting unit 72 is coupled between the half-operating voltage hAVDD and the operating voltage AVDD; the second stage of level shifting unit 73 is coupled between the ground voltage AGND and the half-operating voltage hAVDD; the first stage of level shifting unit 71 is coupled to the second stage of level shifting unit 72.
As shown in FIG. 2, the first stage of level shifting unit 71 includes a first transistor M1, a second transistor M2 . . . and a twelfth transistor M12. The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the ninth transistor M9, and tenth transistor M10 are N-type MOSFETs; the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, and twelfth transistor M12 are P-type MOSFETs.
The second stage of level shifting unit 72 includes a thirteenth transistor M13, a fourteenth transistor M14 . . . and an eighteenth transistor M18. The thirteenth transistor M13 and the fourteenth transistor M14 are N-type MOSFETs; the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18 are P-type MOSFETs.
The second stage of level shifting unit 73 includes a nineteenth transistor M19, a twentieth transistor M20 . . . and a twenty-fourth transistor M24. The nineteenth transistor M19 and the twentieth transistor M20 are N-type MOSFETs; the twenty-first transistor M21, the twenty-second transistor M22, the twenty-third transistor M23, and the twenty-fourth transistor M24 are P-type MOSFETs.
Input terminals IN and INB of the first stage of level shifting unit 71 have an input voltage range between 0V and 1.5V; output terminals OUTP and OUTPB of the second stage of level shifting unit 72 have an output voltage range between 5V and 10V; output terminals OUTN and OUTNB of the third stage of level shifting unit 73 have an output voltage range between 0V and 5V; the ground voltage AGND is 0V; the operating voltage AVDD is 10V; the half-operating voltage hAVDD is 5V; the first middle voltage VCL1 is 6.5V; the second middle voltage VCL2 is 3.5V.
At first, it is assumed that the input voltages received by the input terminals IN and INB of the first stage of level shifting unit 71 are 0V and 1.5V respectively; the voltage level of the node A is the first middle voltage VCL1; the voltage level of the node B is the half-operating voltage hAVDD; the voltage level of the node C is (the second middle voltage VCL2 plus the threshold voltage VT); the voltage level of the node D is the first middle voltage VCL1; voltage levels of the two output terminals OUTP and OUTPB of the second stage of level shifting unit 72 are the half-operating voltage hAVDD and the operating voltage AVDD respectively; voltage levels of the two output terminals OUTN and OUTNB of the second stage of level shifting unit 73 are the ground voltage AGND and the half-operating voltage hAVDD respectively.
After the input voltage signal is converted and the input voltage received by the input terminal IN becomes 1.5V and the input voltage received by the input terminal INB becomes 0V, the voltage level of the node D is under a signal fighting and lowered from the original first middle voltage VCL1 to (the first middle voltage VCL1 minus the threshold voltage VT), and at last further lowered to (the second middle voltage VCL2 plus the threshold voltage VT), so that the eleventh transistor M11 is switched on and the node B is charged from the half-operating voltage hAVDD to the first middle voltage VCL1. Afterward, the eighth transistor M8 is switched on and the node C is charged from (the second middle voltage VCL2 plus the threshold voltage VT) to (the half-operating voltage hAVDD plus the threshold voltage VT), and at last further charged to the first middle voltage VCL1, so that the tenth transistor M10 is switched on and the node A is discharged from the first middle voltage VCL1 to the half-operating voltage hAVDD. The node A and the node B output the voltage signals V2 and V1 to the second stage of level shifting unit 72 respectively to be converted to another power domain.
It should be noticed that the node C cannot be charged until the voltage level of the node D is lowered to (the first middle voltage VCL1 minus the threshold voltage VT); therefore, there will be a time difference between the signal conversion time of the node C and the signal conversion time of the node D; that is to say, the signal conversion times of the node C and the node D cannot be synchronous; therefore, the signal conversion times of the node A and the node B cannot be synchronous with the signal conversion times of the two output terminals OUTP and OUTPB of the second stage of level shifting unit 72.
On the other hand, compared to the output voltage signals of the two output terminals OUTP and OUTPB of the second stage of level shifting unit 72 being boosted by two stages of level shifting circuit to reach the target voltage range of the power domain of the second stage of level shifting unit 72, the output voltage signals of the two output terminals OUTN and OUTNB of the second stage of level shifting unit 73 only needs to be boosted by one stage of level shifting circuit to reach the target voltage range of the power domain of the second stage of level shifting unit 73. Therefore, the signal conversion output time needed by the two output terminals OUTN and OUTNB of the second stage of level shifting unit 73 will be shorter than that needed by the two output terminals OUTP and OUTPB of the second stage of level shifting unit 72. In other words, the signal conversion output time of the two output terminals OUTN and OUTNB of the second stage of level shifting unit 73 is not synchronous with that of the two output terminals OUTP and OUTPB of the second stage of level shifting unit 72.
Above all, it can be found that in the level shifter 7 of the conventional driving circuit, the signal conversion times of the output terminals OUTP, OUTPB, OUTN, and OUTNB of the second stage of level shifting units 72 and 73 fail to be synchronous; therefore, the multi-power domain signal level-shifting efficiency and the performance of the driving circuit of the display will be seriously affected accordingly.